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Rev Log message Author Age Path
28 adjust G port signalling to current T420 TB implementation arniml 6771d 08h /
27 connect missing input direction for IO G arniml 6771d 08h /
26 fix org for page 11 in COP420 code arniml 6771d 08h /
25 fix wrong aisc commands arniml 6771d 09h /
24 finalize test arniml 6771d 10h /
23 finalize test arniml 6772d 01h /
22 finish test arniml 6772d 09h /
21 include t420 system and testbench arniml 6772d 10h /
20 initial check-in arniml 6772d 10h /
19 moved elements to separate design unit tb_elems arniml 6772d 11h /
18 initial check-in arniml 6772d 11h /
17 remove direct specification of cpu type arniml 6773d 10h /
16 enabled t420 support arniml 6773d 10h /
15 initial check-in arniml 6773d 10h /
14 t420 hierarchies added arniml 6773d 10h /
13 hand-down clock divider option arniml 6780d 06h /
12 fix sensitivity list arniml 6781d 06h /
11 renamed to rtl arniml 6781d 07h /
10 renamed t400_por configuration to rtl arniml 6781d 07h /
9 initial check-in arniml 6781d 07h /

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