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Rev Log message Author Age Path
67 explicitly select clock divider 4 arniml 6714d 16h /
66 explicitly select clock divider 8 arniml 6714d 16h /
65 add global signals for testbench instrumentation arniml 6714d 16h /
64 add fail reporting for port d arniml 6714d 16h /
63 initial check-in arniml 6714d 16h /
62 int target added arniml 6714d 16h /
61 initial check-in arniml 6716d 19h /
60 connect cko_i to bit 2 of IN bus arniml 6718d 11h /
59 check CKO in general purpose configuration arniml 6718d 11h /
58 consider IN port arniml 6719d 10h /
57 consider CKO and IN port arniml 6719d 10h /
56 drive IN port arniml 6719d 10h /
55 routi CKO to t400_core arniml 6719d 10h /
54 use to_X01 for primary input bus arniml 6719d 10h /
53 use to_X01 for G input arniml 6719d 10h /
52 + reset neg_edge flip-flops to '1'
-> after por, a 1-to-0 edge is required to trigger the latches initially
+ use to_X01
arniml 6719d 10h /
51 initial check-in arniml 6719d 10h /
50 initial check-in arniml 6719d 12h /
49 io_in added arniml 6720d 11h /
48 instructions ININ and INIL implemented arniml 6720d 11h /

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