URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 103

Rev	Log message	Author	Age	Path
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7394d 18h	/
102	update for changes in address space of external memory	arniml	7394d 18h	/
101	assert p2_read_p2_o when expander port is read	arniml	7394d 18h	/
100	reorder data_o generation	arniml	7394d 18h	/
99	initial check-in	arniml	7394d 18h	/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7394d 19h	/
97	initial check-in	arniml	7394d 19h	/
96	select dedicated directorie(s) for regression	arniml	7395d 16h	/
95	check counter inactivity	arniml	7395d 16h	/
94	initial check-in	arniml	7395d 16h	/
93	add support for line coverage evaluation with gcov	arniml	7395d 17h	/
92	work around bug in Quartus II 4.0	arniml	7395d 17h	/
91	fix edge detector bug for counter	arniml	7395d 17h	/
90	intial check-in	arniml	7395d 17h	/
89	initial check-in	arniml	7409d 14h	/
88	allow memory bank switching during interrupts	arniml	7410d 16h	/
87	abort gracfullt if memory bank switching does not work	arniml	7410d 16h	/
86	update notice about expander port instructions	arniml	7410d 21h	/
85	initial check-in	arniml	7410d 21h	/
84	add if_timing module	arniml	7416d 12h	/