OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 106

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 clean-up use of ea_i arniml 7380d 13h /
105 initial check-in
describe bugs of release 0.1 BETA
arniml 7382d 22h /
104 add white_box directory to test suite arniml 7383d 20h /
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data
arniml 7383d 20h /
102 update for changes in address space of external memory arniml 7383d 20h /
101 assert p2_read_p2_o when expander port is read arniml 7383d 20h /
100 reorder data_o generation arniml 7383d 20h /
99 initial check-in arniml 7383d 20h /
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7383d 21h /
97 initial check-in arniml 7383d 21h /
96 select dedicated directorie(s) for regression arniml 7384d 18h /
95 check counter inactivity arniml 7384d 18h /
94 initial check-in arniml 7384d 18h /
93 add support for line coverage evaluation with gcov arniml 7384d 19h /
92 work around bug in Quartus II 4.0 arniml 7384d 19h /
91 fix edge detector bug for counter arniml 7384d 19h /
90 intial check-in arniml 7384d 19h /
89 initial check-in arniml 7398d 15h /
88 allow memory bank switching during interrupts arniml 7399d 17h /
87 abort gracfullt if memory bank switching does not work arniml 7399d 17h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.