URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

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Rev	Log message	Author	Age	Path
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	7071d 04h	/
177	Implement db_dir_o glitch-safe	arniml	7071d 04h	/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	7071d 04h	/
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	7072d 07h	/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	7072d 07h	/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	7072d 08h	/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7101d 04h	/
171	remove obsolete output stack_high_o	arniml	7102d 04h	/
170	intermediate update	arniml	7103d 11h	/
169	initial check-in	arniml	7103d 16h	/
168	change address range of wb_master	arniml	7103d 16h	/
167	simplify address range: - configuration range - Wishbone range	arniml	7103d 16h	/
166	assign default for state_s	arniml	7105d 08h	/
165	add component wb_master.vhd	arniml	7106d 07h	/
164	initial check-in	arniml	7106d 07h	/
163	add bug Wrong clock applied to T0	arniml	7107d 06h	/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7107d 06h	/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7138d 11h	/
160	add others to case statement	arniml	7259d 07h	/
159	fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0	arniml	7259d 07h	/

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Subversion Repositories t48

[/] - Rev 178

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