URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 182

Rev	Log message	Author	Age	Path
182	intermediate version	arniml	7091d 18h	/
181	fix typo	arniml	7091d 21h	/
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	7100d 03h	/
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	7100d 03h	/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	7101d 15h	/
177	Implement db_dir_o glitch-safe	arniml	7101d 15h	/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	7101d 15h	/
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	7102d 18h	/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	7102d 18h	/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	7102d 18h	/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7131d 14h	/
171	remove obsolete output stack_high_o	arniml	7132d 15h	/
170	intermediate update	arniml	7133d 21h	/
169	initial check-in	arniml	7134d 02h	/
168	change address range of wb_master	arniml	7134d 02h	/
167	simplify address range: - configuration range - Wishbone range	arniml	7134d 02h	/
166	assign default for state_s	arniml	7135d 18h	/
165	add component wb_master.vhd	arniml	7136d 17h	/
164	initial check-in	arniml	7136d 17h	/
163	add bug Wrong clock applied to T0	arniml	7137d 17h	/