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Rev Log message Author Age Path
53 make istrobe visible through testbench package arniml 7417d 16h /
52 + fix bug in PSW[3]
+ read SP properly for dump
arniml 7417d 16h /
51 + implement Port1 and Port2
+ connect T0 and T1
+ return proper program memory contents
arniml 7417d 16h /
50 This commit was manufactured by cvs2svn to create tag 'import'. 7422d 17h /
49 Imported sources arniml 7422d 17h /
48 update copyright notice arniml 7422d 17h /
47 initial check-in arniml 7422d 17h /
46 fix test arniml 7424d 15h /
45 remove unused signals arniml 7424d 15h /
44 default assignment for aux_carry_o arniml 7424d 16h /
43 fix sensitivity list arniml 7425d 16h /
42 change test values that match better to the test case arniml 7425d 19h /
41 expand PATH arniml 7425d 19h /
40 rework adder and force resource sharing between ADD, INC and DEC arniml 7425d 19h /
39 initial check-in arniml 7427d 22h /
38 add measures to implement XCHD arniml 7427d 22h /
37 add dump_compare support arniml 7427d 22h /
36 make calculation of expected value more readable arniml 7427d 23h /
35 initial check-in arniml 7430d 16h /
34 fix test wrt AC arniml 7433d 17h /

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