URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 87

Rev	Log message	Author	Age	Path
87	abort gracfullt if memory bank switching does not work	arniml	7381d 11h	/
86	update notice about expander port instructions	arniml	7381d 16h	/
85	initial check-in	arniml	7381d 16h	/
84	add if_timing module	arniml	7387d 08h	/
83	connect if_timing to P2 output of T48	arniml	7387d 08h	/
82	check expander timings	arniml	7387d 08h	/
81	initial check-in	arniml	7387d 12h	/
80	added if_timing	arniml	7387d 12h	/
79	add if_timing module	arniml	7387d 12h	/
78	adjust external timing of BUS	arniml	7387d 12h	/
77	move from std_logic_arith to numeric_std	arniml	7388d 05h	/
76	initial check-in	arniml	7388d 08h	/
75	remove obsolete design unit	arniml	7388d 08h	/
74	enhance pass/fail detection	arniml	7388d 17h	/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7388d 17h	/
72	removed superfluous signal from sensitivity list	arniml	7388d 17h	/
71	add T8039 and its testbench	arniml	7394d 09h	/
70	clean test cell before make	arniml	7394d 09h	/
69	fix name of istrobe	arniml	7394d 09h	/
68	connect T0 and T1 to P1	arniml	7394d 09h	/