URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 90

Rev	Log message	Author	Age	Path
90	intial check-in	arniml	7396d 07h	/
89	initial check-in	arniml	7410d 04h	/
88	allow memory bank switching during interrupts	arniml	7411d 06h	/
87	abort gracfullt if memory bank switching does not work	arniml	7411d 06h	/
86	update notice about expander port instructions	arniml	7411d 11h	/
85	initial check-in	arniml	7411d 11h	/
84	add if_timing module	arniml	7417d 02h	/
83	connect if_timing to P2 output of T48	arniml	7417d 02h	/
82	check expander timings	arniml	7417d 02h	/
81	initial check-in	arniml	7417d 07h	/
80	added if_timing	arniml	7417d 07h	/
79	add if_timing module	arniml	7417d 07h	/
78	adjust external timing of BUS	arniml	7417d 07h	/
77	move from std_logic_arith to numeric_std	arniml	7417d 23h	/
76	initial check-in	arniml	7418d 03h	/
75	remove obsolete design unit	arniml	7418d 03h	/
74	enhance pass/fail detection	arniml	7418d 11h	/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7418d 11h	/
72	removed superfluous signal from sensitivity list	arniml	7418d 12h	/
71	add T8039 and its testbench	arniml	7424d 04h	/