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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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Rev Log message Author Age Path
117 Fixed the top level and connected the entire project. creep 5717d 19h /
116 Changed the module instantiation into the dot form. creep 5717d 20h /
115 Renamed the signal control. It is mem_rw now. creep 5717d 20h /
114 Created a global timescale file for the project. Added to the top module. creep 5717d 20h /
113 Timescale was unified. gabrieloshiro 5717d 20h /
112 Created a global timescale file for the project. creep 5717d 20h /
111 Performed some linting after coding was finished. creep 5718d 12h /
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5718d 13h /
109 PLA and PLP are coded and simulated. creep 5718d 16h /
108 PHA and PHP are coded and simulated. creep 5718d 16h /
107 The RTS instruction is working fine. Coded and simulated. creep 5718d 17h /
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5718d 17h /
105 The RTI instruction is working fine. Coded and simulated. creep 5718d 18h /
104 The BRK instruction is working. The reset vector was tested also. creep 5718d 19h /
103 Some early modifications to support the special stack instructions. creep 5719d 13h /
102 Some early modifications to support the special stack instructions. creep 5719d 16h /
101 Absolute indirect addressing mode is coded and simulated. creep 5719d 19h /
100 IDY WRITE TYPE instructions are coded and simulated. creep 5719d 20h /
99 Only Package.v should be used. creep 5719d 21h /
98 Updated status and some comments. creep 5719d 21h /

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