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Rev Log message Author Age Path
118 The top level name was in uppercase. The correct is lowercase. creep 6091d 06h /
117 Fixed the top level and connected the entire project. creep 6091d 06h /
116 Changed the module instantiation into the dot form. creep 6091d 07h /
115 Renamed the signal control. It is mem_rw now. creep 6091d 07h /
114 Created a global timescale file for the project. Added to the top module. creep 6091d 07h /
113 Timescale was unified. gabrieloshiro 6091d 07h /
112 Created a global timescale file for the project. creep 6091d 07h /
111 Performed some linting after coding was finished. creep 6091d 23h /
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 6092d 00h /
109 PLA and PLP are coded and simulated. creep 6092d 03h /
108 PHA and PHP are coded and simulated. creep 6092d 04h /
107 The RTS instruction is working fine. Coded and simulated. creep 6092d 04h /
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 6092d 05h /
105 The RTI instruction is working fine. Coded and simulated. creep 6092d 05h /
104 The BRK instruction is working. The reset vector was tested also. creep 6092d 07h /
103 Some early modifications to support the special stack instructions. creep 6093d 00h /
102 Some early modifications to support the special stack instructions. creep 6093d 03h /
101 Absolute indirect addressing mode is coded and simulated. creep 6093d 06h /
100 IDY WRITE TYPE instructions are coded and simulated. creep 6093d 07h /
99 Only Package.v should be used. creep 6093d 08h /

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