URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 129

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Rev	Log message	Author	Age	Path
129	RTL and e files are truly linked now. Some very early coverage is done.	creep	5766d 01h	/
128	$write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized.	gabrieloshiro	5766d 05h	/
127	Testbench created. Simulation is almost done! Everything seems to be working fine.	gabrieloshiro	5766d 06h	/
126	Added a wrapper for the ALU. This file creates the clock for Specman.	creep	5766d 06h	/
125	All files are linked to each other. RTL is still not linked through hdl_path()	creep	5766d 22h	/
124	All signals are mapped on the BFM and MON using the SIG_MAP.	creep	5767d 00h	/
123	Added all the eRM files.	creep	5767d 01h	/
122	Adding alu_mon.e	creep	5767d 01h	/
121	Adding formal verification folder.	creep	5767d 02h	/
120	Added some extra commentaries.	creep	5768d 01h	/
119	removing old file.	creep	5768d 04h	/
118	The top level name was in uppercase. The correct is lowercase.	creep	5768d 05h	/
117	Fixed the top level and connected the entire project.	creep	5768d 06h	/
116	Changed the module instantiation into the dot form.	creep	5768d 06h	/
115	Renamed the signal control. It is mem_rw now.	creep	5768d 06h	/
114	Created a global timescale file for the project. Added to the top module.	creep	5768d 06h	/
113	Timescale was unified.	gabrieloshiro	5768d 06h	/
112	Created a global timescale file for the project.	creep	5768d 06h	/
111	Performed some linting after coding was finished.	creep	5768d 22h	/
110	All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage.	creep	5768d 23h	/

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Subversion Repositories t6507lp

[/] - Rev 129

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