URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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Rev	Log message	Author	Age	Path
133	Checker updated. ADD's and AND's should be working fine.	creep	5764d 11h	/
132	Added a .e file containing the opcodes. Other files modified as well. Chebeing written.	creep	5764d 12h	/
131	Added a checker for i/o comparison.	creep	5767d 08h	/
130	Added alu_input.e to the repository.	creep	5767d 10h	/
129	RTL and e files are truly linked now. Some very early coverage is done.	creep	5767d 10h	/
128	$write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized.	gabrieloshiro	5767d 14h	/
127	Testbench created. Simulation is almost done! Everything seems to be working fine.	gabrieloshiro	5767d 15h	/
126	Added a wrapper for the ALU. This file creates the clock for Specman.	creep	5767d 16h	/
125	All files are linked to each other. RTL is still not linked through hdl_path()	creep	5768d 08h	/
124	All signals are mapped on the BFM and MON using the SIG_MAP.	creep	5768d 10h	/
123	Added all the eRM files.	creep	5768d 10h	/
122	Adding alu_mon.e	creep	5768d 11h	/
121	Adding formal verification folder.	creep	5768d 11h	/
120	Added some extra commentaries.	creep	5769d 11h	/
119	removing old file.	creep	5769d 14h	/
118	The top level name was in uppercase. The correct is lowercase.	creep	5769d 15h	/
117	Fixed the top level and connected the entire project.	creep	5769d 15h	/
116	Changed the module instantiation into the dot form.	creep	5769d 15h	/
115	Renamed the signal control. It is mem_rw now.	creep	5769d 16h	/
114	Created a global timescale file for the project. Added to the top module.	creep	5769d 16h	/

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Subversion Repositories t6507lp

[/] - Rev 133

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