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Rev Log message Author Age Path
74 The file now describes who is doing what. creep 5775d 04h /
73 Added schedule file into the readme file. creep 5775d 04h /
72 Project management folder. creep 5775d 05h /
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5775d 05h /
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 5779d 01h /
69 Added signal origin/destination. creep 5779d 03h /
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5779d 03h /
67 File name change to lowercase. HAL says so! creep 5779d 05h /
66 File name change to lowercase. HAL says so! creep 5779d 05h /
65 Now the blocks are connected. gabrieloshiro 5780d 00h /
64 Constant were wrong. gabrieloshiro 5780d 00h /
63 Fixed several HAL warnings. Still plenty to do. creep 5780d 00h /
62 The DUT file name changed. creep 5780d 00h /
61 File name change to lowercase. HAL says so! creep 5780d 01h /
60 File name change. HAL says so! creep 5780d 01h /
59 I`ve fixed some latch creation. gabrieloshiro 5780d 01h /
58 ALU with all opcodes ready for simulation. gabrieloshiro 5780d 02h /
57 A very simple testbench that checks the execution for a single instruction, i.e. no memory. creep 5780d 02h /
56 Several changes in the output logic to respect the pipelining. creep 5780d 02h /
55 ALU has all opcodes now! Comments inside ALU are completely wrong. gabrieloshiro 5780d 03h /

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