URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 84

Rev	Log message	Author	Age	Path
84	X and Y register are passed from ALU to FSM.	gabrieloshiro	5629d 22h	/
83	Completed HAL checking. All the relevant warnings and errors were removed.	creep	5629d 23h	/
82	Did some checking with HAL and fixed 20+ warnings and errors.	creep	5630d 15h	/
81	Decimal mode (BCD) is working.	gabrieloshiro	5630d 15h	/
80	Grouping some instructions that have the same behavioral.	gabrieloshiro	5630d 16h	/
79	ALU testbench added.	gabrieloshiro	5630d 17h	/
78	ZPG coded and simulated.	creep	5630d 17h	/
77	ZPG coded. Simulation is halfway.	creep	5630d 18h	/
76	ABS write instructions were not simulated. Also added some initial ZPG simulation.	creep	5630d 18h	/
75	First working version!	gabrieloshiro	5630d 18h	/
74	The file now describes who is doing what.	creep	5630d 18h	/
73	Added schedule file into the readme file.	creep	5630d 18h	/
72	Project management folder.	creep	5630d 18h	/
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	5630d 18h	/
70	Fixed several timing. Registered outputs working. Only three adressing modes coded, the previous coding was erased.	creep	5634d 15h	/
69	Added signal origin/destination.	creep	5634d 17h	/
68	The FSM module is now parametrized. Also, several changes were made to remove most of the lint warnings.	creep	5634d 17h	/
67	File name change to lowercase. HAL says so!	creep	5634d 19h	/
66	File name change to lowercase. HAL says so!	creep	5634d 19h	/
65	Now the blocks are connected.	gabrieloshiro	5635d 14h	/