URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 86

Rev	Log message	Author	Age	Path
86	Zero page indexed mode is working fine.	creep	6096d 15h	/
85	alu_x and alu_y variables created.	gabrieloshiro	6096d 20h	/
84	X and Y register are passed from ALU to FSM.	gabrieloshiro	6096d 20h	/
83	Completed HAL checking. All the relevant warnings and errors were removed.	creep	6096d 20h	/
82	Did some checking with HAL and fixed 20+ warnings and errors.	creep	6097d 12h	/
81	Decimal mode (BCD) is working.	gabrieloshiro	6097d 13h	/
80	Grouping some instructions that have the same behavioral.	gabrieloshiro	6097d 13h	/
79	ALU testbench added.	gabrieloshiro	6097d 14h	/
78	ZPG coded and simulated.	creep	6097d 14h	/
77	ZPG coded. Simulation is halfway.	creep	6097d 15h	/
76	ABS write instructions were not simulated. Also added some initial ZPG simulation.	creep	6097d 15h	/
75	First working version!	gabrieloshiro	6097d 15h	/
74	The file now describes who is doing what.	creep	6097d 15h	/
73	Added schedule file into the readme file.	creep	6097d 15h	/
72	Project management folder.	creep	6097d 15h	/
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	6097d 16h	/
70	Fixed several timing. Registered outputs working. Only three adressing modes coded, the previous coding was erased.	creep	6101d 12h	/
69	Added signal origin/destination.	creep	6101d 14h	/
68	The FSM module is now parametrized. Also, several changes were made to remove most of the lint warnings.	creep	6101d 14h	/
67	File name change to lowercase. HAL says so!	creep	6101d 16h	/