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Rev Log message Author Age Path
27 Xilinx SSRAM, initial release jesus 7930d 02h /
26 Fixed instruction timing for POP and DJNZ jesus 7943d 18h /
25 IX/IY timing and ADC/SBC fix jesus 7945d 04h /
24 no message jesus 7951d 00h /
23 Fixed T2Write jesus 7951d 01h /
22 Added 8080 top level jesus 7951d 01h /
21 no message jesus 7956d 00h /
20 Updated for new T80s generic jesus 7956d 00h /
19 Initial version jesus 7956d 00h /
18 Added T2Write generic jesus 7956d 06h /
17 Removed write through jesus 7957d 23h /
16 no message jesus 7958d 03h /
15 Added clock enable and fixed IM 2 jesus 7965d 02h /
14 Changed to Xilinx ROM jesus 7984d 14h /
13 Initial import jesus 7984d 14h /
12 Initial import jesus 7984d 14h /
11 Added support for XST jesus 7984d 15h /
10 Added dummy files jesus 7984d 15h /
9 Initial import jesus 7986d 02h /
8 Fixed refresh address and DJNZ instruction jesus 7986d 02h /

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