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Rev Log message Author Age Path
46 Made some bugfixes andreas 7388d 22h /
45 Fixed loopback break generation jesus 8390d 01h /
44 Added some missing features and fixed baud rate generator jesus 8390d 14h /
43 *** empty log message *** jesus 8399d 01h /
42 Fixed bus req/ack cycle jesus 8399d 02h /
41 Removed UNISIM library jesus 8399d 02h /
40 Cleanup jesus 8399d 02h /
39 Added -n option and component declaration jesus 8426d 23h /
38 Added Leonardo .ucf generation jesus 8426d 23h /
37 Changed to single register file jesus 8427d 02h /
36 Added component declaration jesus 8427d 02h /
35 Release 0242 jesus 8433d 14h /
34 Updated for ISE 5.1 jesus 8433d 19h /
33 Fixed typo jesus 8443d 11h /
32 Fixed for ISE 5.1 jesus 8443d 11h /
31 Fixed generic name error jesus 8446d 13h /
30 Changed to xilinx specific RAM jesus 8452d 13h /
29 Fixed (IX/IY+d) timing and added all GB op-codes jesus 8452d 13h /
28 Adapted for zxgate jesus 8453d 13h /
27 Xilinx SSRAM, initial release jesus 8453d 13h /

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