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Rev Log message Author Age Path
42 Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it. julius 5884d 09h /
41 Removed duplicate or1200_defines.v and timescale.v files julius 5884d 11h /
40 Change name of file and module of orpsoc_top module julius 5884d 12h /
39 Removed auto logging of processor state, added option to enable it in makefile, documented way the tests are done in makefile and that should probably be moved to some readme at some point julius 5884d 13h /
38 Actually that last fix caused another bug. This, and the original, are now fixed. Dhrystone ICDC passes julius 5884d 15h /
37 Hacked a bug fix - probably due to DCache bugs which are due to be fixed - dhrystone-icdc test still does not complete julius 5885d 12h /
36 Couple of makefile updates julius 5885d 15h /
35 Fixed or1200_defines confusion julius 5885d 15h /
34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5885d 16h /
33 Fixed up software linker script, and changed placement of vectors where necessary. Icarus tests up to mul-nocache-O2 works but had to re-enable MAC in or1200 julius 5887d 04h /
32 Looks like basic icarus tests passing. Todo is a list of timeouts for the rtl sim julius 5887d 08h /
31 Further progress with orpsoc test setup julius 5887d 08h /
30 Updating bench julius 5889d 13h /
29 Fixed address decode on 64bit platforms julius 5889d 18h /
28 Added branch and jump relative calculations in or32 idecode tool julius 5889d 18h /
27 Adding OpenRISC instruction decode tool code julius 5889d 20h /
26 Adding testbench and makefile update julius 5890d 17h /
25 Adding sw dir PROPERLY julius 5890d 19h /
24 Attempting to put in sw dir properly julius 5890d 19h /
23 adding sw directory julius 5890d 19h /

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