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Rev	Log message	Author	Age	Path
59	Adding sw support library uart files	julius	5667d 20h	/
58	Further documentation in the main makefile	julius	5667d 21h	/
57	A better explanation at top of main sim makefile	julius	5668d 18h	/
56	OR1k sim tests now implemented and working	julius	5668d 18h	/
55	Systemc vcd file name based on test name which is passed via command line when the executable is run	julius	5668d 20h	/
54	Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at	julius	5668d 21h	/
53	verilator test loop in makefile - same results as icarus	julius	5669d 11h	/
52	Enabled own printf function using UART as output	julius	5669d 11h	/
51	Added SystemC Uart model	julius	5672d 01h	/
50	Tracing enabled on Verilator model	julius	5672d 15h	/
49	Verilator model now builds OK.	julius	5672d 23h	/
48	Closer to working verilator build	julius	5673d 16h	/
47	Basic verilator model getting closer. Included more modules from the example by Jeremy Bennett. Final cplusplus executable from verilator output fails to link properly	julius	5673d 19h	/
46	Flash memory now also disabled when SDRAM disabled, which is by default. Ethernet now enabled by defining USE_ETHERNET, otherwise it is disabled by default. Default icarus tests now very fast due to this	julius	5674d 23h	/
45	Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default	julius	5675d 16h	/
44	Beginnings of verilator build - much still to do but the design can now at least be verilated	julius	5681d 20h	/
43	Added some verilator lint controls, made icarus script much more concise. First stage of verilation now works	julius	5682d 00h	/
42	Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.	julius	5682d 15h	/
41	Removed duplicate or1200_defines.v and timescale.v files	julius	5682d 18h	/
40	Change name of file and module of orpsoc_top module	julius	5682d 19h	/

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[/] - Rev 59

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