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Rev Log message Author Age Path
60 Bit of polish on main makefile and removed some unncessary library calls in software makefile julius 6023d 11h /
59 Adding sw support library uart files julius 6023d 14h /
58 Further documentation in the main makefile julius 6023d 14h /
57 A better explanation at top of main sim makefile julius 6024d 12h /
56 OR1k sim tests now implemented and working julius 6024d 12h /
55 Systemc vcd file name based on test name which is passed via command line when the executable is run julius 6024d 14h /
54 Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at julius 6024d 15h /
53 verilator test loop in makefile - same results as icarus julius 6025d 05h /
52 Enabled own printf function using UART as output julius 6025d 05h /
51 Added SystemC Uart model julius 6027d 19h /
50 Tracing enabled on Verilator model julius 6028d 08h /
49 Verilator model now builds OK. julius 6028d 17h /
48 Closer to working verilator build julius 6029d 09h /
47 Basic verilator model getting closer. Included more modules from the example by Jeremy Bennett. Final cplusplus executable from verilator output fails to link properly julius 6029d 13h /
46 Flash memory now also disabled when SDRAM disabled, which is by default. Ethernet now enabled by defining USE_ETHERNET, otherwise it is disabled by default. Default icarus tests now very fast due to this julius 6030d 17h /
45 Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default julius 6031d 10h /
44 Beginnings of verilator build - much still to do but the design can now at least be verilated julius 6037d 13h /
43 Added some verilator lint controls, made icarus script much more concise. First stage of verilation now works julius 6037d 18h /
42 Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it. julius 6038d 09h /
41 Removed duplicate or1200_defines.v and timescale.v files julius 6038d 12h /

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