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Rev Log message Author Age Path
171 Added TestBench_verilator.cpp and TestBench_verilog.v diegovalverde 4805d 08h /
170 diegovalverde 4809d 02h /
169 Adding scripts folder diegovalverde 4811d 19h /
168 Addign example files diegovalverde 4811d 19h /
167 Added variables to add generic number of cores diegovalverde 4811d 20h /
166 diegovalverde 4811d 20h /
165 No log files shall be created by defualt diegovalverde 4812d 23h /
164 Getting rid of warnings diegovalverde 4813d 19h /
163 Moved this to the simulation folder diegovalverde 4819d 22h /
162 Adding modified Makefile diegovalverde 4819d 22h /
161 diegovalverde 4819d 22h /
160 Adding testbench folder diegovalverde 4820d 23h /
159 Adding makefile diegovalverde 4820d 23h /
158 Adding source code that icarus likes. diegovalverde 4820d 23h /
157 Adding a project that correctly simulates using Icarus verilog diegovalverde 4820d 23h /
156 Cosmetic change diegovalverde 4829d 22h /
155 renaming folder diegovalverde 4829d 22h /
154 Renaming folder to RTL, now all files in a flat structure. diegovalverde 4829d 22h /
153 Removing this folder, it is no longer needed diegovalverde 4829d 22h /
152 Temporary change to folder structure diegovalverde 4829d 22h /

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