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Rev Log message Author Age Path
181 diegovalverde 4796d 05h /
180 Fixing bug diegovalverde 4796d 06h /
179 Fix from previous commit diegovalverde 4797d 04h /
178 Latest changes to try to fix bug with many triangles. WIP diegovalverde 4797d 04h /
177 Adding changed I missed from previous commit diegovalverde 4810d 04h /
176 Added support for parametrized number of TMEM banks. Also changes cross-bar by some ugly muxes, so that it runs on Verilator. diegovalverde 4812d 05h /
175 Fixing warnings from Verilator diegovalverde 4818d 06h /
174 Removed combinatorial loops detectd by verilator. diegovalverde 4823d 16h /
173 Adding file top.v diegovalverde 4823d 16h /
172 Modifying to use new testbed by default diegovalverde 4823d 16h /
171 Added TestBench_verilator.cpp and TestBench_verilog.v diegovalverde 4823d 16h /
170 diegovalverde 4827d 09h /
169 Adding scripts folder diegovalverde 4830d 03h /
168 Addign example files diegovalverde 4830d 03h /
167 Added variables to add generic number of cores diegovalverde 4830d 03h /
166 diegovalverde 4830d 03h /
165 No log files shall be created by defualt diegovalverde 4831d 07h /
164 Getting rid of warnings diegovalverde 4832d 02h /
163 Moved this to the simulation folder diegovalverde 4838d 05h /
162 Adding modified Makefile diegovalverde 4838d 05h /

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