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Rev Log message Author Age Path
185 Adding scripts diegovalverde 4775d 07h /
184 Fixing Square root diegovalverde 4776d 05h /
183 Fixing previous errors. diegovalverde 4778d 02h /
182 diegovalverde 4779d 23h /
181 diegovalverde 4780d 01h /
180 Fixing bug diegovalverde 4780d 01h /
179 Fix from previous commit diegovalverde 4781d 00h /
178 Latest changes to try to fix bug with many triangles. WIP diegovalverde 4781d 00h /
177 Adding changed I missed from previous commit diegovalverde 4794d 00h /
176 Added support for parametrized number of TMEM banks. Also changes cross-bar by some ugly muxes, so that it runs on Verilator. diegovalverde 4796d 01h /
175 Fixing warnings from Verilator diegovalverde 4802d 02h /
174 Removed combinatorial loops detectd by verilator. diegovalverde 4807d 12h /
173 Adding file top.v diegovalverde 4807d 12h /
172 Modifying to use new testbed by default diegovalverde 4807d 12h /
171 Added TestBench_verilator.cpp and TestBench_verilog.v diegovalverde 4807d 12h /
170 diegovalverde 4811d 05h /
169 Adding scripts folder diegovalverde 4813d 23h /
168 Addign example files diegovalverde 4813d 23h /
167 Added variables to add generic number of cores diegovalverde 4813d 23h /
166 diegovalverde 4813d 23h /

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