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Rev Log message Author Age Path
13 update document, add how to encrypt homer.hsing 4275d 08h /
12 add test vector generator ~ ~ homer.hsing 4319d 06h /
11 Update document. Add graph of core structure homer.hsing 4357d 01h /
10 Update document. Changes in section performance: "128 bytes"->"128 bits", and throughput. homer.hsing 4389d 09h /
9 Change timing of testbench, following timing constraints homer.hsing 4399d 04h /
8 Update Xilinx ISE constraint file homer.hsing 4399d 05h /
7 Upload specification homer.hsing 4401d 08h /
6 Add AES-192. Less memory bit in lookup_table. homer.hsing 4402d 22h /
5 AES 256 :) homer.hsing 4403d 20h /
4 Add "_128" suffix to aes_128 related module to prevent name conflict homer.hsing 4403d 22h /
3 Add synthesis constraints, testbench simulation script homer.hsing 4404d 22h /
2 Release under Apache License v2.0 homer.hsing 4404d 23h /
1 The project and the structure was created root 4405d 21h /

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