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Rev	Log message	Author	Age	Path
21	The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it.	earlz	4575d 22h	/
20	fuck it. All sorts of broken, will try to fix it tomorrow	earlz	4576d 22h	/
19	Got beginning of core/decoder for the CPU	earlz	4576d 23h	/
18	Finished memory controller	earlz	4580d 09h	/
17	Added fetch component for fetching from memory to instruction register Added additional testing for carryover to make sure it's correct	earlz	4580d 23h	/
16	Renamed incdec to carryover (see design for why). carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.	earlz	4584d 01h	/
15	Added README, LICENSE, and the (so far not created) incdec component	earlz	4585d 22h	/
14	Added ALU with all the operations we'll need. Synthesizes as well trivially	earlz	4586d 07h	/
13	Forgot about the new library I added	earlz	4586d 09h	/
12	registerfile has ports for every register now makefile now uses GHW file format for gtkwave instead of VCD	earlz	4586d 10h	/
11	Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge	earlz	4589d 23h	/
10	Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs	earlz	4590d 00h	/
9	Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench	earlz	4590d 07h	/
8	Added blockram for inferring actual block RAM. Now we need a memory controller, not a crappy memory emulation thing	earlz	4591d 07h	/
7	Changed memory to fix bound check error Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)	earlz	4591d 08h	/
6	Reworked memory code to hopefully synthesize better	earlz	4591d 13h	/
5	Modified registerfile to be dual-port for both read and write	earlz	4592d 00h	/
4	Added internal memory interface Updated design	earlz	4592d 08h	/
3	Updated registerfile to have 2 read ports Added super rough design document mainly just for brainstorming	earlz	4593d 00h	/
2	Initial commit	earlz	4593d 01h	/

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Subversion Repositories tinycpu

[/] - Rev 21

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