OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] - Rev 46

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
46 This commit was manufactured by cvs2svn to create branch 'restruc1'. 7463d 18h /
45 Added negedge version of top ghutchis 7463d 18h /
44 Updated run script for better dump control ghutchis 7463d 21h /
43 Fixed assembly routines for blk mem copy test ghutchis 7486d 10h /
42 Added decode of OUT (##),A instruction
Removed dump-by-default and added DUMP_START define
ghutchis 7486d 10h /
41 Added random-read value port ghutchis 7488d 14h /
40 Added random-read port and block memory instruction test ghutchis 7488d 14h /
39 Added checksum port definitions, and test for block-OUT instructions ghutchis 7488d 15h /
38 Added command-line options for help (-h) and run with instruction decode (-d) ghutchis 7490d 07h /
37 Added new I/O registers for testing block I/O ghutchis 7490d 07h /
36 Removed default instruction decode ghutchis 7490d 07h /
35 Updated IO registers to add checksum and increment-on-read registers
used for testing block I/O instructions.
ghutchis 7490d 19h /
34 Created test for block I/O instructions ghutchis 7490d 19h /
33 Added missing IncDec controls to OUTI/OUTD instructions ghutchis 7491d 16h /
32 Added "bintr" basic interrupt test, which tests Z80 interrupt mode 1. ghutchis 7506d 18h /
31 1) Added environment support for Z80 op decode in log file.
2) Fixed env support for interrupt generation and clearing
ghutchis 7506d 18h /
30 Added HTML version of docs ghutchis 7509d 18h /
29 Added references ghutchis 7509d 18h /
28 Added code to initialize RAM to all 00 at environment start-up time. ghutchis 7509d 18h /
27 Modified tvs80 test to run from a ROM image, and work with the
standard environment.
ghutchis 7509d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.