OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] - Rev 58

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
58 Made TX path async
Made TX clock input instead of output
ghutchis 7140d 13h /
57 Optimized read-back of data using INIR instruction ghutchis 7140d 20h /
56 Updated env for simple_gmii with async clk ghutchis 7140d 20h /
55 Added documentation of core area and the simple GMII interface block. ghutchis 7140d 23h /
54 Test program for network interface ghutchis 7142d 19h /
53 Added environment hooks for using and testing the GMII interface ghutchis 7142d 20h /
52 Added simple GMII-like interface for testing ghutchis 7142d 20h /
51 More restructuring-related code ghutchis 7142d 20h /
50 Basic synthesis script for timing/area comparison ghutchis 7157d 23h /
49 New file list for restructured core ghutchis 7157d 23h /
48 Created branch for restructuring effort ghutchis 7157d 23h /
47 This commit was manufactured by cvs2svn to create branch 'restruc2'. 7157d 23h /
46 This commit was manufactured by cvs2svn to create branch 'restruc1'. 7157d 23h /
45 Added negedge version of top ghutchis 7157d 23h /
44 Updated run script for better dump control ghutchis 7158d 02h /
43 Fixed assembly routines for blk mem copy test ghutchis 7180d 15h /
42 Added decode of OUT (##),A instruction
Removed dump-by-default and added DUMP_START define
ghutchis 7180d 15h /
41 Added random-read value port ghutchis 7182d 19h /
40 Added random-read port and block memory instruction test ghutchis 7182d 19h /
39 Added checksum port definitions, and test for block-OUT instructions ghutchis 7182d 20h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.