OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] - Rev 75

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.
ghutchis 7059d 13h /
74 Changed default for T2Write to be 1, to match expected behavior for
most users.
ghutchis 7059d 14h /
73 Added RC4 encrypt/decrypt test ghutchis 7071d 09h /
72 Added copyright header ghutchis 7071d 09h /
71 Ported UART from T80 ghutchis 7132d 13h /
70 Added test for T16450 UART ghutchis 7183d 07h /
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7183d 07h /
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.
ghutchis 7191d 08h /
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.
ghutchis 7191d 08h /
66 Modified top level testbench to reflect changes in simple_gmii block ghutchis 7191d 08h /
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic
ghutchis 7191d 08h /
64 Created rgen script and expanded available register types ghutchis 7192d 07h /
63 Added simple regression script. -r command runs all tests (serially),
-c command checks results after all tests have completed.
ghutchis 7226d 11h /
62 Reset timeout counter whenever a message is printed ghutchis 7226d 11h /
61 Added timeout disable for large buf sizes ghutchis 7226d 12h /
60 Added ifdef TV80_REFRESH, to remove refresh logic by default. Also
ran untabify to remove tabs from source code.
ghutchis 7226d 12h /
59 Added lib for generating MPU interfaces ghutchis 7226d 12h /
58 Made TX path async
Made TX clock input instead of output
ghutchis 7265d 23h /
57 Optimized read-back of data using INIR instruction ghutchis 7266d 06h /
56 Updated env for simple_gmii with async clk ghutchis 7266d 06h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.