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Rev Log message Author Age Path
56 thre irq should be cleared only when being source of interrupt. mohor 8246d 14h /
55 some synthesis bugs fixed gorban 8247d 02h /
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8247d 15h /
53 Scratch register define added. mohor 8248d 16h /
52 Scratch register added gorban 8249d 05h /
51 Igor fixed break condition bugs gorban 8249d 05h /
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8253d 10h /
49 committed the debug interface file gorban 8255d 03h /
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8256d 03h /
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8261d 05h /
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8262d 02h /
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8263d 03h /
44 fixed more typo bugs gorban 8277d 03h /
43 lsr1r error fixed. mohor 8277d 10h /
42 ti_int_pnd error fixed. mohor 8277d 10h /
41 ti_int_d error fixed. mohor 8277d 10h /
40 Synthesis bugs fixed. Some other minor changes gorban 8279d 12h /
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8281d 10h /
38 small update to test interrupts gorban 8282d 07h /
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8282d 07h /

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