URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8230d 03h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8230d 08h	/
59	MSR register fixed.	mohor	8233d 05h	/
58	After reset modem status register MSR should be reset.	mohor	8233d 08h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8234d 08h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8234d 08h	/
55	some synthesis bugs fixed	gorban	8234d 20h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8235d 09h	/
53	Scratch register define added.	mohor	8236d 09h	/
52	Scratch register added	gorban	8236d 22h	/
51	Igor fixed break condition bugs	gorban	8236d 22h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8241d 03h	/
49	committed the debug interface file	gorban	8242d 21h	/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8243d 20h	/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8248d 23h	/
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8249d 20h	/
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8250d 21h	/
44	fixed more typo bugs	gorban	8264d 20h	/
43	lsr1r error fixed.	mohor	8265d 03h	/
42	ti_int_pnd error fixed.	mohor	8265d 03h	/

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Subversion Repositories uart16550

[/] - Rev 61

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