URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
68	lsr[7] was not showing overrun errors.	mohor	8323d 04h	/
67	Missing declaration of rf_push_q fixed.	mohor	8330d 04h	/
66	rx push changed to be only one cycle wide.	mohor	8330d 04h	/
65	Warnings fixed (unused signals removed).	mohor	8331d 09h	/
64	Warnings cleared.	mohor	8331d 09h	/
63	Synplicity was having troubles with the comment.	mohor	8331d 10h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8332d 08h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8333d 03h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8333d 07h	/
59	MSR register fixed.	mohor	8336d 04h	/
58	After reset modem status register MSR should be reset.	mohor	8336d 07h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8337d 07h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8337d 07h	/
55	some synthesis bugs fixed	gorban	8337d 19h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8338d 08h	/
53	Scratch register define added.	mohor	8339d 08h	/
52	Scratch register added	gorban	8339d 21h	/
51	Igor fixed break condition bugs	gorban	8339d 21h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8344d 02h	/
49	committed the debug interface file	gorban	8345d 20h	/

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Subversion Repositories uart16550

[/] - Rev 68

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