URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
74	tf_overrun signal was disabled since it was not used	gorban	8313d 23h	/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8320d 22h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8334d 06h	/
71	Removed confusing comment	gorban	8345d 19h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8351d 03h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8359d 18h	/
68	lsr[7] was not showing overrun errors.	mohor	8363d 01h	/
67	Missing declaration of rf_push_q fixed.	mohor	8370d 01h	/
66	rx push changed to be only one cycle wide.	mohor	8370d 01h	/
65	Warnings fixed (unused signals removed).	mohor	8371d 06h	/
64	Warnings cleared.	mohor	8371d 07h	/
63	Synplicity was having troubles with the comment.	mohor	8371d 07h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8372d 06h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8373d 00h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8373d 05h	/
59	MSR register fixed.	mohor	8376d 01h	/
58	After reset modem status register MSR should be reset.	mohor	8376d 05h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8377d 04h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8377d 05h	/
55	some synthesis bugs fixed	gorban	8377d 16h	/

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Subversion Repositories uart16550

[/] - Rev 74

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