URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	8155d 15h	/
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8308d 21h	/
77	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		8308d 21h	/
76	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		8308d 21h	/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8308d 21h	/
74	tf_overrun signal was disabled since it was not used	gorban	8313d 23h	/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8320d 22h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8334d 05h	/
71	Removed confusing comment	gorban	8345d 18h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8351d 03h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8359d 17h	/
68	lsr[7] was not showing overrun errors.	mohor	8363d 01h	/
67	Missing declaration of rf_push_q fixed.	mohor	8370d 01h	/
66	rx push changed to be only one cycle wide.	mohor	8370d 01h	/
65	Warnings fixed (unused signals removed).	mohor	8371d 05h	/
64	Warnings cleared.	mohor	8371d 06h	/
63	Synplicity was having troubles with the comment.	mohor	8371d 07h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8372d 05h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8372d 23h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8373d 04h	/

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Subversion Repositories uart16550

[/] - Rev 79

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