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Rev Log message Author Age Path
14 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5785d 15h /
13 UART16750: Added automatic flow control hasw 5798d 15h /
12 UART16750: Updated stimuli script with automatic flow control tests hasw 5798d 15h /
11 UART16750: Removed dependency from std_logic_unsigned hasw 5798d 16h /
10 UART16750: Removed dependency from std_logic_unsigned hasw 5798d 16h /
9 Registered control line outputs hasw 5807d 17h /
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5807d 17h /
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5808d 22h /
6 THR empty interrupt register connected to RST hasw 5808d 23h /
5 Removed old component hasw 5809d 17h /
4 Removed swap file hasw 5809d 18h /
3 This commit was manufactured by cvs2svn to create tag 'Import'. 5809d 18h /
2 Imported sources hasw 5809d 18h /
1 Standard project directories initialized by cvs2svn. 5809d 18h /

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