OpenCores
URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] - Rev 17

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
17 New directory structure. root 5738d 05h /
16 UART16750: Added example project hasw 5758d 17h /
15 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5767d 19h /
14 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5768d 21h /
13 UART16750: Added automatic flow control hasw 5781d 22h /
12 UART16750: Updated stimuli script with automatic flow control tests hasw 5781d 22h /
11 UART16750: Removed dependency from std_logic_unsigned hasw 5781d 22h /
10 UART16750: Removed dependency from std_logic_unsigned hasw 5781d 23h /
9 Registered control line outputs hasw 5791d 00h /
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5791d 00h /
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5792d 05h /
6 THR empty interrupt register connected to RST hasw 5792d 05h /
5 Removed old component hasw 5793d 00h /
4 Removed swap file hasw 5793d 01h /
3 This commit was manufactured by cvs2svn to create tag 'Import'. 5793d 01h /
2 Imported sources hasw 5793d 01h /
1 Standard project directories initialized by cvs2svn. 5793d 01h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.