URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] - Rev 20

Rev	Log message	Author	Age	Path
20	UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state	hasw	5820d 03h	/
19	Added old uploaded documents to new repository.	root	5836d 07h	/
18	Added old uploaded documents to new repository.	root	5836d 13h	/
17	New directory structure.	root	5836d 13h	/
16	UART16750: Added example project	hasw	5857d 00h	/
15	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5866d 02h	/
14	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5867d 04h	/
13	UART16750: Added automatic flow control	hasw	5880d 05h	/
12	UART16750: Updated stimuli script with automatic flow control tests	hasw	5880d 05h	/
11	UART16750: Removed dependency from std_logic_unsigned	hasw	5880d 05h	/
10	UART16750: Removed dependency from std_logic_unsigned	hasw	5880d 06h	/
9	Registered control line outputs	hasw	5889d 07h	/
8	Make memory read in generic FIFO model synchronous for optimized used with XST	hasw	5889d 07h	/
7	Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST	hasw	5890d 12h	/
6	THR empty interrupt register connected to RST	hasw	5890d 13h	/
5	Removed old component	hasw	5891d 07h	/
4	Removed swap file	hasw	5891d 08h	/
3	This commit was manufactured by cvs2svn to create tag 'Import'.		5891d 08h	/
2	Imported sources	hasw	5891d 08h	/
1	Standard project directories initialized by cvs2svn.		5891d 08h	/