OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] - Rev 12

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
12 Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism. motilito 4644d 07h /
11 VHDL version:
- Add a request-grant mechanism. This will permit to use it on a shared bus without any bus contention.
- Improve the test benches.
- Automate the launching of test benches.
- Fix a bug in 'uartRx.vhd'.
- Reorganize a little bit the directory structure.
smuller 4645d 23h /
10 VHDL version: corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. smuller 4737d 21h /
9 Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. motilito 4739d 08h /
8 Updated core description document to include Lattice device synthesis results. motilito 4960d 13h /
7 Updated the Scilab script for Scilab 5.3 version. Previous versions might not work. motilito 4981d 21h /
6 Commit VHDL description source with basic test benches smuller 5231d 07h /
5 Add structure for VHDL (verilog similar tree). smuller 5243d 00h /
4 Corrected some problems in the binary mode protocol test bench.
Updated documentation.
motilito 5337d 22h /
3 motilito 5384d 04h /
2 Uploaded the initial project version. motilito 5384d 06h /
1 The project and the structure was created root 5386d 23h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.