URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.	motilito	4655d 20h	/
11	VHDL version: - Add a request-grant mechanism. This will permit to use it on a shared bus without any bus contention. - Improve the test benches. - Automate the launching of test benches. - Fix a bug in 'uartRx.vhd'. - Reorganize a little bit the directory structure.	smuller	4657d 11h	/
10	VHDL version: corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	smuller	4749d 09h	/
9	Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	motilito	4750d 20h	/
8	Updated core description document to include Lattice device synthesis results.	motilito	4972d 01h	/
7	Updated the Scilab script for Scilab 5.3 version. Previous versions might not work.	motilito	4993d 10h	/
6	Commit VHDL description source with basic test benches	smuller	5242d 19h	/
5	Add structure for VHDL (verilog similar tree).	smuller	5254d 12h	/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5349d 11h	/
3		motilito	5395d 17h	/
2	Uploaded the initial project version.	motilito	5395d 18h	/
1	The project and the structure was created	root	5398d 11h	/