URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] - Rev 7

Rev	Log message	Author	Age	Path
7	Updated the Scilab script for Scilab 5.3 version. Previous versions might not work.	motilito	4833d 11h	/
6	Commit VHDL description source with basic test benches	smuller	5082d 21h	/
5	Add structure for VHDL (verilog similar tree).	smuller	5094d 14h	/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5189d 12h	/
3		motilito	5235d 18h	/
2	Uploaded the initial project version.	motilito	5235d 20h	/
1	The project and the structure was created	root	5238d 13h	/