URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] - Rev 16

Rev	Log message	Author	Age	Path
16	Adding testbench for wishbone slave module	leonardoaraujo.santos	4675d 13h	/
15	Taking out some warnings and transparent latches from the design	leonardoaraujo.santos	4675d 14h	/
14	Fixing some warnings... Adding wishbone slave	leonardoaraujo.santos	4676d 10h	/
13	Working on uart_control testbench... also applying some fixes...	leonardoaraujo.santos	4676d 11h	/
12	Working on the communication blocks	leonardoaraujo.santos	4676d 12h	/
11	Adding uart_communication_block	leonardoaraujo.santos	4676d 15h	/
10	Working on the control unit part	leonardoaraujo.santos	4676d 19h	/
9	Adding Control unit for uart block	leonardoaraujo.santos	4677d 06h	/
8	Solving some bugs in baud_generator.vhd	leonardoaraujo.santos	4677d 17h	/
7	Remember to clean project files	leonardoaraujo.santos	4678d 13h	/
6	Adding baud generator	leonardoaraujo.santos	4678d 13h	/
5	Adding sequential division (32 cycles per 32 bit word)	leonardoaraujo.santos	4683d 15h	/
4	Working on receiver	leonardoaraujo.santos	4685d 15h	/
3	Deleting unused files and changing tests	leonardoaraujo.santos	4685d 16h	/
2	Starting here ....	leonardoaraujo.santos	4685d 17h	/
1	The project and the structure was created	root	4686d 08h	/