URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] - Rev 19

Rev	Log message	Author	Age	Path
19	Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd)	leonardoaraujo.santos	4544d 15h	/
18	sdsd	leonardoaraujo.santos	4544d 21h	/
17	Working on slave testbench and fixing some bugs	leonardoaraujo.santos	4544d 23h	/
16	Adding testbench for wishbone slave module	leonardoaraujo.santos	4544d 23h	/
15	Taking out some warnings and transparent latches from the design	leonardoaraujo.santos	4545d 00h	/
14	Fixing some warnings... Adding wishbone slave	leonardoaraujo.santos	4545d 20h	/
13	Working on uart_control testbench... also applying some fixes...	leonardoaraujo.santos	4545d 21h	/
12	Working on the communication blocks	leonardoaraujo.santos	4545d 22h	/
11	Adding uart_communication_block	leonardoaraujo.santos	4546d 00h	/
10	Working on the control unit part	leonardoaraujo.santos	4546d 04h	/
9	Adding Control unit for uart block	leonardoaraujo.santos	4546d 16h	/
8	Solving some bugs in baud_generator.vhd	leonardoaraujo.santos	4547d 02h	/
7	Remember to clean project files	leonardoaraujo.santos	4547d 23h	/
6	Adding baud generator	leonardoaraujo.santos	4547d 23h	/
5	Adding sequential division (32 cycles per 32 bit word)	leonardoaraujo.santos	4553d 01h	/
4	Working on receiver	leonardoaraujo.santos	4555d 01h	/
3	Deleting unused files and changing tests	leonardoaraujo.santos	4555d 01h	/
2	Starting here ....	leonardoaraujo.santos	4555d 03h	/
1	The project and the structure was created	root	4555d 18h	/