URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] - Rev 20

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Rev	Log message	Author	Age	Path
20	Finishing at least the tests on testbench.... Was good to verify that the uart_control should be redesigned to allow concurrent receive and to clean the code...	leonardoaraujo.santos	4722d 11h	/
19	Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd)	leonardoaraujo.santos	4722d 12h	/
18	sdsd	leonardoaraujo.santos	4722d 18h	/
17	Working on slave testbench and fixing some bugs	leonardoaraujo.santos	4722d 20h	/
16	Adding testbench for wishbone slave module	leonardoaraujo.santos	4722d 20h	/
15	Taking out some warnings and transparent latches from the design	leonardoaraujo.santos	4722d 21h	/
14	Fixing some warnings... Adding wishbone slave	leonardoaraujo.santos	4723d 17h	/
13	Working on uart_control testbench... also applying some fixes...	leonardoaraujo.santos	4723d 18h	/
12	Working on the communication blocks	leonardoaraujo.santos	4723d 19h	/
11	Adding uart_communication_block	leonardoaraujo.santos	4723d 21h	/
10	Working on the control unit part	leonardoaraujo.santos	4724d 01h	/
9	Adding Control unit for uart block	leonardoaraujo.santos	4724d 13h	/
8	Solving some bugs in baud_generator.vhd	leonardoaraujo.santos	4724d 23h	/
7	Remember to clean project files	leonardoaraujo.santos	4725d 20h	/
6	Adding baud generator	leonardoaraujo.santos	4725d 20h	/
5	Adding sequential division (32 cycles per 32 bit word)	leonardoaraujo.santos	4730d 22h	/
4	Working on receiver	leonardoaraujo.santos	4732d 22h	/
3	Deleting unused files and changing tests	leonardoaraujo.santos	4732d 22h	/
2	Starting here ....	leonardoaraujo.santos	4733d 00h	/
1	The project and the structure was created	root	4733d 15h	/

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Subversion Repositories uart_block

[/] - Rev 20

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