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URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

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21 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments		 aborga 4818d 22h /
20 MODIFIED: block diagram with new namings for uart din and dout aborga 4818d 22h /
19 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments		 aborga 4818d 22h /
18 MODIFIED: removed unnecessary libraries aborga 4819d 19h /
17 DELETED: useless package folder aborga 4819d 21h /
16 MODIFIED: added

uart_rst_i : in std_logic;
uart_leds_o : out std_logic_vector(7 downto 0);

in the entity declaration		 aborga 4819d 21h /
15 UPDATED: email address aborga 4821d 19h /
14 ADDED: backup of the project description aborga 4822d 11h /
13 UDATED: simple documentation aborga 4822d 13h /
12 ADDED: original documentation of the UART_16550 core by LeFevre aborga 4822d 14h /
11 ADDED: Block diagram of the UART_FPGA_slow_control_main_diagram
1) pdf format
2) Microsoft visio source file (sorry...)		 aborga 4822d 14h /
10 MODIFIED: added further description and examples aborga 4822d 20h /
9 ADDED: HowToSVN.txt to handle repositories with windows Tortoise SVN aborga 4822d 20h /
8 ADDED: some more documentation

1) screenshot of a full read and write sequence with questasim
2) example hex commands to be sent via RealTerm		 aborga 4822d 21h /
7 MODIFIED: line 359 baudrate set aborga 4822d 21h /
6 CREATED: how to change baudrate text file aborga 4822d 21h /
5 aborga 4822d 22h /
4 DELETED: moved to a code folder aborga 4822d 22h /
3 CREATED: first code upload! :) aborga 4822d 22h /
2 CREATED: first code upload! :) aborga 4822d 22h /

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