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Rev Log message Author Age Path
10 All project files in ZIP. alfoltran 7488d 00h /
9 All project files in one ZIP file. alfoltran 7502d 07h /
8 Verilog defines file for testbench. alfoltran 7502d 07h /
7 All files in '.zip'. alfoltran 7505d 04h /
6 Task in5 correction: no ACK for length zero packet. alfoltran 7505d 04h /
5 Function in5 correction: no ACK for length zero packet. alfoltran 7505d 04h /
4 USB1.1 Testbench Documentation alfoltran 7505d 04h /
3 All projects files in '.zip'. alfoltran 7506d 03h /
2 Initial version in OpenCores.org (2004/04/10 - 19:22GMT) alfoltran 7506d 04h /
1 Standard project directories initialized by cvs2svn. 7506d 04h /

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