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Rev Log message Author Age Path
12 Correction of the out2, out4 and out6 function DATA MISMATCH ERROR message. alfoltran 7377d 02h /
11 Correction of the out2, out4 and out6 function DATA MISMATCH ERROR message.
Modification in out4 and out6 functions for XILINX TIMED SIMULATION.
alfoltran 7377d 02h /
10 All project files in ZIP. alfoltran 7377d 02h /
9 All project files in one ZIP file. alfoltran 7391d 09h /
8 Verilog defines file for testbench. alfoltran 7391d 09h /
7 All files in '.zip'. alfoltran 7394d 06h /
6 Task in5 correction: no ACK for length zero packet. alfoltran 7394d 06h /
5 Function in5 correction: no ACK for length zero packet. alfoltran 7394d 06h /
4 USB1.1 Testbench Documentation alfoltran 7394d 07h /
3 All projects files in '.zip'. alfoltran 7395d 06h /
2 Initial version in OpenCores.org (2004/04/10 - 19:22GMT) alfoltran 7395d 06h /
1 Standard project directories initialized by cvs2svn. 7395d 06h /

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