URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] - Rev 117

Rev	Log message	Author	Age	Path
117	reset polarity in mig_b.prj for ddr2 was wrong , should be high	ultro	2920d 23h	/
116	fix path of the axi rom module	ultro	2934d 18h	/
115	update for synth slack	ultro	2935d 12h	/
114	update cosmetic	ultro	2935d 13h	/
113	updates to take acu appart	ultro	2935d 13h	/
112	Added the prj missing files	ultro	2939d 02h	/
111	added comment	ultro	2955d 12h	/
110	updated MCS files to be downloaded to nexys4 DDR	ultro	2955d 12h	/
109	update for nexys 4 ddr	ultro	2955d 12h	/
108	update xdc for nexys 4 ddr	ultro	2955d 12h	/
107	crossbar update	ultro	2955d 13h	/
106	update core netlist	ultro	2955d 13h	/
105	migration nexys ddr	ultro	2955d 14h	/
104	iadd rstgen and clk wiard for ddr nexys4 TOP	ultro	2962d 14h	/
103	commit top for 128mbyte nexys4 ddr version	ultro	2972d 04h	/
102	committed 128mbytes boot code for nexys4 ddr	ultro	2972d 04h	/
101	add ddr interface mig7 xilinx xci ip	ultro	2972d 17h	/
100	add crossbar for nexys4 ddr with 128megabyte ram window	ultro	2972d 17h	/
99	remove phy_intn from xdc constraints as it is not used inside design wi th etherlite.	ultro	3014d 02h	/
98	update tbench and add mii to rmii converter ip from xilinx	ultro	3014d 12h	/