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Subversion Repositories v586

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Rev Log message Author Age Path
19 added readme file on uart16750 project usage and original files ultro 3696d 01h /
18 added original uart16750 files ultro 3696d 01h /
17 change makefile for verilog simulation with 16750 ultro 3696d 01h /
16 added gpio and second uart to ucf ultro 3696d 01h /
15 update mem files for booting at 57600 bauds with 16750 ultro 3696d 01h /
14 update RTL with bug fix for prefetch and dual aurt 16750 addition ultro 3696d 01h /
13 added 16750 uart netlist ultro 3696d 01h /
12 delete 16450 ultro 3696d 01h /
11 commit nex mcs ultro 3725d 00h /
10 delete ultro 3725d 00h /
9 update readme ultro 3725d 00h /
8 update boot for faster copy from spi flash to sram ultro 3725d 01h /
7 update bug on prefetch length grant 10 -> 11 ultro 3725d 01h /
6 removed extra file ultro 3728d 12h /
5 initial commit ultro 3728d 19h /
4 initial commit ultro 3728d 19h /
3 initial commit ultro 3728d 19h /
2 initial commit ultro 3728d 19h /
1 The project and the structure was created root 3729d 03h /

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