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Rev Log message Author Age Path
19 DFF with async clear and set for Altera cycloneIV unneback 5379d 15h /
18 ADDR and DATA width set to 8 resp 32 unneback 5380d 05h /
17 based on updated versatile counter unneback 5384d 04h /
16 changed power of two style unneback 5647d 14h /
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5651d 07h /
14 added PDF unneback 5695d 14h /
13 adr update unneback 5696d 16h /
12 no mux on dual port mem read unneback 5709d 09h /
11 name conflict
wptr1 changed to wptr1_cnt etc
unneback 5709d 12h /
10 rptr2 unneback 5709d 13h /
9 unneback 5715d 09h /
8 unneback 5715d 09h /
7 unneback 5715d 09h /
6 unneback 5715d 12h /
5 async compare for fifo full and empty unneback 5715d 12h /
4 unneback 5715d 16h /
3 unneback 5715d 17h /
2 unneback 5715d 17h /
1 The project was created and the structure was created root 5717d 11h /

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