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Rev Log message Author Age Path
29 ACTEL syn define unneback 5213d 02h /
28 ACTEL async dual way FIFO unneback 5220d 11h /
27 initial commit, dual way simplex FIFO unneback 5221d 03h /
26 added ACTEL synthesis directive as define, +ACTEL unneback 5221d 03h /
25 DFF SR as separate logic unneback 5360d 22h /
24 updated fifo interfaces with re/rd and we/wr unneback 5361d 13h /
23 unneback 5364d 01h /
22 async fifo with multiple queues unneback 5364d 02h /
21 added DFF SR unneback 5377d 23h /
20 unneback 5378d 07h /
19 DFF with async clear and set for Altera cycloneIV unneback 5379d 13h /
18 ADDR and DATA width set to 8 resp 32 unneback 5380d 03h /
17 based on updated versatile counter unneback 5384d 01h /
16 changed power of two style unneback 5647d 11h /
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5651d 04h /
14 added PDF unneback 5695d 11h /
13 adr update unneback 5696d 13h /
12 no mux on dual port mem read unneback 5709d 06h /
11 name conflict
wptr1 changed to wptr1_cnt etc
unneback 5709d 09h /
10 rptr2 unneback 5709d 10h /

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