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Rev Log message Author Age Path
32 fixed SYN directives marcus.erlandsson 5115d 09h /
31 port map unneback 5186d 01h /
30 port map unneback 5186d 02h /
29 ACTEL syn define unneback 5193d 23h /
28 ACTEL async dual way FIFO unneback 5201d 09h /
27 initial commit, dual way simplex FIFO unneback 5202d 00h /
26 added ACTEL synthesis directive as define, +ACTEL unneback 5202d 00h /
25 DFF SR as separate logic unneback 5341d 20h /
24 updated fifo interfaces with re/rd and we/wr unneback 5342d 11h /
23 unneback 5344d 23h /
22 async fifo with multiple queues unneback 5345d 00h /
21 added DFF SR unneback 5358d 21h /
20 unneback 5359d 04h /
19 DFF with async clear and set for Altera cycloneIV unneback 5360d 10h /
18 ADDR and DATA width set to 8 resp 32 unneback 5361d 00h /
17 based on updated versatile counter unneback 5364d 23h /
16 changed power of two style unneback 5628d 08h /
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5632d 02h /
14 added PDF unneback 5676d 09h /
13 adr update unneback 5677d 11h /

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